The present invention relates to a circuit switching method and apparatus for time division network with various transmission speeds, and more particularly, to a method and apparatus for switching time division multiplexed signals having a variety of transmission speeds.
Conventionally, as a method for switching time division multiplexed signals having a variety of transmission speeds, there is a method of performing a switching operation wherein a time division switch is used with a low speed circuit being as switching units, and a high speed circuit is assumed to be composed of a plurality of low speed circuits, as described in a document entitled "A Consideration on Wideband Switching System" by Shimoe, Murakami and Endo, in paper of The Institute of Electronics and Communication on Engineers of Japan, SE84-33, published in 1984. Also, as shown in the same document, there is a method wherein a switch for a high speed circuit, and a switch for a low speed circuit are disposed in parallel.
As for the method of performing a switching wherein a time division switch is used with a low speed circuit being as switching units and a high speed circuit is assumed to be composed of a plurality of low speed circuits, it cannot be applied unless there is a relationship where a high speed circuit transmission speed is an integer multiple of a low speed circuit transmission speed. In this case, it is possible to achieve a switching at various transmission speeds by means of a time division switch which defines the greatest common measure of the two classes of the circuit transmission speeds as a unit. However, in this case, a switching cycle becomes long, and correspondingly a signal delay is increased, which results in an increase of a necessary memory capacity.
For this reason, in a communication circuit where switches presenting a large signal delay exist in multiple stages between the transmission and reception terminals, an immense signal delay occurs between the transmission and reception terminals. On the other hand, the method in which a plurality of types of switches are disposed in parallel exhibits a small signal delay, however, requires a plurality of switches, whereby the apparatus scale is enlarged.